In circuits for high frequency applications, the unwanted series resistance and capacitance across the input terminals of a device must be reduced. One of the high frequency devices is a high electron mobility transistor (HEMT) where input signals are applied between the gate and source. To reduce the series resistance, the cross section of the gate metal should be maintained even when its length is reduced for short channel devices. To reduce the capacitance, the lateral areas of the gate electrode facing the source and drain should be minimized. This is achieved by adopting a two sections gate electrode structure (100) as depicted in FIG. 1(a), which shows a simplified schematic diagram of a HEMT (100) having a substrate (101), a channel layer (102), a source (103), a drain (104) and a gate (105). The gate (105) has a stem portion (105s) and a head portion (105h), the dimension of the stem portion of the gate contacting the channel layer is defined as the gate length or channel length (105Ls) which is made close to 100 nm or smaller in order to achieve high frequency performance. Whereas the head portion length (105Lh) is made substantially larger than the gate length (105Ls) to reduce the resistance of the gate in the direction of perpendicular to the direction of channel length and parallel to the surface of the substrate. Such a gate with the head portion substantially longer than that of the stem portion is often called a T-gate. It may be possible that the head portion is not aligned to the stem portion symmetrically to reduce further the capacitance to the source. Such a gate with the misaligned head portion is often called inverted L-gate.
The fabrication of these T-gate or inverted L-gate is normally made by a lift-off process in order to avoid the interaction of etching chemicals with the channel layer on the substrate, which is often based on GaAs and related materials. The lift-off process is depicted in FIG. 1(b)-1(d). To simplify the explanation, the drain, source and channel layer are not shown in these figures. On a semiconductor substrate (101), a first photoresist (or resist) layer (112) with a first resist layer thickness (112t) and a second resist layer (113) having a second resist layer thickness (113t) are applied. Material of the first resist layer is selected to be different from that of the second resist layer to minimize intermixing between these two resist layers. First, the second resist layer (113) is exposed to a second UV light beam through a second photomask pattern and developed to form a second cavity (113c). After a cleaning and drying step, the first resist layer is exposed to a first UV light beam through a first photomask pattern and then developed to form a first cavity (112c) of a width (112w). During the creation of the second cavity (113c), the exposure and developing conditions are selected so that top portion width (113wt) of the second cavity is smaller than the bottom portion width (113wb) to facilitate lift-off after metal layer deposition. As shown in FIG. 1(b), the second cavity widths (113wt and 113wb) is selected to be larger than the first cavity width (112w) in order to form the stem portion and head portion of the gate. After cleaning and drying, the semiconductor substrate (101) with the first resist layer and the second resist layer is loaded into a vacuum chamber to deposit metal layer for forming of the gate (105). Due to the nature of deposition, layer of gate metal (115a, 115b, FIG. 1(c)) is also deposited on the second resist layer (113). Gate thickness (105th) is controlled to be less than the second resist layer thickness (113t) so that there is no connection between the gate (105) and the layer of gate metal (115a, 115b) on the second resist layer. The semiconductor substrate (101) with the first resist layer (112), the second resist layer (113) and the deposited gate (105) and the layer of gate metal (115a, 115b) is immersed in a solvent to dissolve the first resist layer and the second resist layer. The layer of gate metal (115a, 115b) will be detached from the semiconductor substrate. After a cleaning and drying step, the fabrication of the T-gate (105) on the semiconductor substrate (101) as shown in FIG. 1(d) is completed.
In the above described method, the materials for the first resist layer (112) should have slower developing property compared to that for the second resist layer (113). FIG. 2 shows schematically the developing property of the exposed first resist layer (Curve A) and that of the second resist layer (Curve B) in a developer B used to develop the second resist layer (113). It is noted that the thickness of the second resist layer at tD≈100 seconds is effectively zero whereas the decrease in the thickness of the first resist layer, ΔthA is almost negligible. Therefore, the second resist layer (113) can be developed without affecting the integrity of the first resist layer (112).
The prior art processing steps involving two separate photomasks are illustrated in FIG. 3(a)-3(d). As depicted in FIG. 3(a), a first resist layer (112) of thickness (112t) is coated on a semiconductor substrate (101) and baked. This is followed by the coating and baking of a second resist layer (113) of thickness (113t). A second light beam (120) having a second light beam length (120L) is illuminated on the second resist layer (113) through a second photomask (121) with a second window of width (121w). After exposure, the semiconductor substrate with the resist layers is immersed in a developer B to develop the second resist layer (113) and to form a second cavity (113c) with a top portion width (113wt), as indicated in FIG. 3(b). After rinsing and drying, a first light beam (125) having a first light beam length (125L), defined by a first photomask (126) with a first window width (126w), is illuminated on the first resist layer (112). After exposure, the semiconductor substrate with the resist layers is developed in a developer A to develop the first resist layer and to form a first cavity (112c) with a first cavity width (112w), as indicated in FIG. 3(d). After rinsing and drying, the semiconductor substrate with the first cavity (112c) and the second cavity (113c) is ready for the deposition of gate metal layer.
It is thus clear that in order to form the first cavity and a second cavity to define the gate structure using the prior art method, a first photomask, a second photomask, a first resist layer and a second resist layer of a different material are needed. Furthermore, precise alignment is required when applying the first photomask and the second photomask. In order to simplify the formation process, a method using only one photomask to create the cavities can be very beneficial.